Embodiments of the inventive concept relate to cache coherent systems, and more particularly, to cache coherent systems including a master-side filter capable of performing a security check. Embodiments of the inventive concept also relate to data processing systems including at least one of cache coherent system including a master-side filter capable of performing a security check.
“Cache coherency” or “cache coherence” is a term used to describe a consistency of data and/or data operation(s) between two or more local caches respectively included in clients (or processors) in a shared memory system. When each of the clients includes its own local cache and multiple clients share one or more memory, the problem of cache coherence may occur as one or more caches associated with one or more clients is updated.
Previously, when a cache coherence problem occurs (or might occur), the shared memory system may perform certain operations to achieve cache coherence or prevent loss of cache coherence. Accordingly, when the shared memory system writes data to a shared memory resource (e.g., a cache), the overall latency of the write operation may increase.
By way of example, it is assumed that a system includes; a cache coherent interface, a central processing unit (CPU) connected to the cache coherent interface, and a graphics processing unit (GPU) connected to the cache coherent interface. It is further assumed that the CPU, operating in a non-secure mode, outputs a snoop request to the GPU and a cache hit occurs for a cache of the GPU. As a result, a cache line (i.e., cache data) stored in the cache may be written back to an external memory device connected to the system. After the write-back operation is completed, the CPU may communicate a command to read the cache line that has been written back to the external memory device to a controller that controls the external memory device. Accordingly, write-back traffic involved in the write-back and memory read request traffic involved in the reading of the cache line stored in the external memory device increases.